1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the simultaneous fabrication of contacts between metal layers and fuse windows reducing masking steps.
2. Description of the Prior Art
Fuses have been employed in semiconductor circuits to allow programming of the operation thereof after one or more processing operations. In some semiconductor circuits, such as DRAMS, redundant circuitry is placed into the chip in a short circuit mode connected by fuses. Then, after testing, redundant bits are programmed to replace "faulty" bits. This programming is accomplished by blowing the fuses for the unwanted connections, typically with a laser.
Some semiconductor devices, such as DRAMS require fuses and interlayer metal contacts. The conventional approach to fabricating fuses and interlevel metal contacts on the same chip requires one mask for etching the via for the interlayer metal contact plus three masks to open the fuse window: (1) etching the interlevel dielectric and intermetal dielectric above the fuse; (2) etching the passivation layer; and (3) opening the polyimide. Multiple masking steps increase processing complexity, add additional alignment tolerances and increase processing time.
The inventors have determined that it would be desirable to simultaneously etch the via and the fuse window. However, the inventors have determined that in order to form a good contact between the lower metal layer (M1) and the upper level metal (M2) in the via, an overetch is required. This overetch reduces the thickness of the interlevel dielectric remaining over the fuse, causing a high rate of fuse failure during a subsequent etch of M2.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,472,901 (Kapoor) teaches a method for forming horizontal fuses in the same deposition step as contacts.
U.S. Pat. No. 5,753,539 (Okazaki) shows a method for forming fuse opening and contact opening using different opening diameters and microloading effects.
U.S. Pat. No. 5,618,750 (Fukuhara) discloses a method for forming fuse openings.
U.S. Pat. No. 5,760,453 (Chen) shows a method for forming a fuse window and an overlying moisture barrier.